These are student research positions currently available.
Research: Wearable mechatronics, IoT, and intelligent biomedical systems, Advisor: Matthew Flavin
Lab details: Flavin Neuromachines Lab
TIGs: Bioengineering, Computer Systems and Software, Electronic Design & Applications, Systems and Controls, Telecommunications
Seeking: PhD Students, 4 positions
Application Due August 31, 2026 to mflavin@gatech.edu
Research keywords: Neuroengineering, IoT, wearables, haptics, education, assistive technologies
Description:
The Flavin Neuromachines Lab is recruiting talented, driven individuals who are interested in leading projects in the areas of neural mechatronics and extended reality for patient care.
Preferred skills include:
-PCB design
-Embedded firmware design
-Experience in cloud backend development
Please contact Prof. Flavin (mflavin@gatech.edu) with a cover letter and CV.
Entry Created: August 19, 2024 at 4:54 am
Research: SoC Framework Development, Advisor: Yingyan (Celine) Lin
Lab details: EIC Lab
TIGs: VLSI Systems and Digital Design
Seeking: Undergraduate Students, MS students, 1 positions
Application Due June 15, 2025 to eic-intern-application@groups.gatech.edu
Research keywords:
Description:
Project Overview
This project involves three main deliverables:
1 SoC Design: Integrate a RocketChip CPU core, a lightweight neural-network (NN) accelerator, and a network-on-chip (NoC).
2 Custom Toolchain: Extend the RISC-V toolchain to compile and link applications that invoke both the CPU and the NN accelerator.
3 Validation Suite: Develop a testbench and representative software workload to verify end-to-end functionality and performance.
Technical Requirements
RocketChip Framework: All CPU and NoC components should be implemented using the RocketChip generator.
NN Accelerator: Implement in SystemC-based HLS with HLSLibs connectivity primitives. Must be synthesizable via Siemens Catapult.
External Interface: Support an AXI-Stream–like protocol for DRAM interactions (e.g., simple DRAM model).
Preferred Skills
1. Proficiency in Verilog and SystemC-based HLS.
2. Familiarity with Siemens Catapult synthesis flows.
3. Basic physical-design experience (beneficial but not mandatory).
Please include “[SoC Framework Development]” in the email title.
Entry Created: April 25, 2025 at 9:30 pm
Research: SystemC-Based Out-of-Order RISC-V CPU Design, Advisor: Yingyan (Celine) Lin
Lab details: EIC Lab
TIGs: VLSI Systems and Digital Design
Seeking: Undergraduate Students, MS students, 1 positions
Application Due June 15, 2025 to eic-intern-application@groups.gatech.edu
Research keywords:
Description:
Project Overview
1. CPU Design: Architect and implement a parameterizable, out-of-order–issue, in-order–commit RV64I/M/A/F/D core in SystemC/HLS.
2. Toolchain Extension: Adapt the RISC-V compiler and linker to recognize and generate code for the custom co-processor and synchronization instructions.
3. Validation Suite: Develop an testbench plus a simple software test to test the system.
Technical Requirements
1. ISA Support: RV64I, M, A, F, D subsets; no virtual-memory or OS support required.
2. Pipeline Features:
– a. Out-of-order issue, in-order commit.
– b. Parameterizable execution-backend count.
– c. Parameterizable Instruction Queue (IQ) depth and Reorder Buffer (ROB) size.
– d. Parameterizable physical register file size.
3. Co-Processor Interface: One custom instruction for co-processor communication.
4. Synchronization: One instruction to synchronize across multiple cores.
5. Memory Subsystem:
– a. Implement a Load-Store Queue (LSQ).
– b. Parameterizable L1 instruction cache, L1 data cache, and unified L2 cache.
– c. AXI-compatible DRAM interface.
6. Implementation:
– a. All implementations should be SystemC with HLSLibs.
– b. Synthesizable via Siemens Catapult and validated through RTL simulation.
Preferred Skills
– Expertise in Verilog and SystemC-based HLS design.
– Experience with basic physical-design flows (preferred, but not required).
Entry Created: April 25, 2025 at 9:33 pm
Research: SystemC-Based Neural Rendering Hardware Design and FPGA Deployment, Advisor: Yingyan (Celine) Lin
Lab details: EIC Lab
TIGs: VLSI Systems and Digital Design
Seeking: Undergraduate Students, MS students, 1 positions
Application Due June 15, 2025 to eic-intern-application@groups.gatech.edu
Research keywords:
Description:
Project Overview
1. Implement modules from recent neural rendering hardware using SystemC
– a. MetaVRain
– – I. Visual Processing Core
– – II. 2D neural engine
– – III. 1D neural engine
PEU
– b. IRIS
– – I. Reconfigurable FP Multiplier
– – II. Hybrid Aligned-Mantissa Adder Tree
– – III. Surface Perception Unit
– – IV. Error Direction Cache
– c. MetaSapiens
– – I. Fov Filter
– – II. Duplication Unit
– – III. Tile Merge Unit
– – IV. Hierarchical Sorting Unit
– – V. Volume Rendering Core
2. Deploy the synthesized modules on FPGA for validation.
3. System integration of hardware modules, Interconnects between modules using HLSlibs
Technical Requirements
1. Familiarity with AXI protocols, Understand burst read/write DRAM when doing system integration
2. Experience with Verilog and HLS hardware design
3. Experience with FPGA design flow, Vivado, Vitis
Preferred Skills
Expertise in Verilog and SystemC-based HLS design
Entry Created: April 25, 2025 at 9:36 pm